The present invention relates to an integrated circuit device for use in an electronic appliance such as a computer. More specifically, the present invention relates to an integrated circuit device which is suitable for accomplishing high velocity signal propagation between logic circuits inside an integrated circuit chip having a large chip size.
Signal transmission between logic circuits inside an integrated circuit chip is generally effected by signal wirings inside the integrated circuit chip using near-end termination. Regarding recent developments, the increase in the signal propagation delay time between the logic circuits inside the integrated circuit chip resulting from the miniaturization of the signal wirings and the increase in the wiring length inside the integrated circuit chip has become a serious problem as the degree of integration density and area of the integrated circuit chip have become increased. Besides a relatively high wiring resistance of the signal wiring inside the integrated circuit chip, this problem can be attributed significantly to the fact that the signal propagation delay time is in proportion to the square of the wiring length when near-end termination is employed as a driving system of the signal wiring.
To reduce the signal propagation delay time, far-end termination capable of higher velocity signal transmission than near-end termination may be employed, in principle. To effect signal transmission by far-end termination, however, the wiring resistance of the signal wiring must be sufficiently lowered. For this reason, far-end termination cannot be applied to driving of the signal wirings inside the integrated circuit chip having a relatively high wiring resistance.
JP-A-59-182540 discloses the technique which disposes signal wirings having a greater width than other wiring channels in partial regions of the wiring channels on the integrated circuit chip so as to reduce the wiring resistance of the signal wiring and to improve a signal transmission velocity. However, this technique is not free of the following problems.
(1) Since wide signal wirings exist in or are limited to a specific region, freedom is low when high velocity signal wirings must be used with respect to arbitrary gate circuits.
(2) Efficiency of use of the channels drops as a whole.
(3) Though the technique can reduce the wiring resistance of the signal wiring, it cannot reduce it to such an extent that far-end termination can be applied. Therefore, the problem that the signal propagation delay time is proportional to the square of the wiring length remains yet to be solved.